performance - How can I improve the speed of my Makefile? -


i building multiple binaries in c++ & cuda couple of files in fortran. found this question , i'm having similar problem. user asked me re-build 3 year old version of repository (before had performed massive migration , renaming) , shocked see how built. impossible / incredibly time consuming determine of changes between version , caused build take friggin' long.

however, noticed in answer's comment aforementioned question:

in particular, remember use := instead of =, := expansion immediately, saves time. – jack kelly mar 23 @ 22:38

are there other suggestions should aware of?

note:

  • i use 'include' paradigm each directory want build has module.mk file directly included 1 , makefile.
  • i use several functions like:

(markdown..)

# # cuda compilation rules #  define cuda-compile-rule   $1: $(call generated-source,$2) \     $(call source-dir-to-build-dir, $(subst .cu,.cubin, $2)) \     $(call source-dir-to-build-dir, $(subst .cu,.ptx, $2))     $(nvcc) $(cubin_arch_flag) $(nvccflags) $(incflags) $(defines) -o $$@ -c $$<    $(call source-dir-to-build-dir, $(subst .cu,.cubin, $2)): $(call generated-source,$2)     $(nvcc) -cubin -xptxas -v $(cubin_arch_flag) $(nvccflags) $(incflags) $(defines) $(smversionflags) -o $$@ $$<    $(call source-dir-to-build-dir, $(subst .cu,.ptx, $2)): $(call generated-source,$2)     $(nvcc) -ptx $(cubin_arch_flag) $(nvccflags) $(incflags) $(defines) $(smversionflags) -o $$@ $$<    $(subst .o,.d,$1): $(call generated-source,$2)     $(nvcc) $(cubin_arch_flag) $(nvccflags) $3 $(target_arch) $(incflags) $(defines) -m $$< | \     $(sed) 's,\($$(notdir $$*)\.o\) *:,$$(dir $$@)\1 $$@: ,' > $$@.tmp     $(mv) $$@.tmp $$@ endef
  • but of these functions used in older version...

lastly: how can determine if it's compilation time or make time slowing things down?

i didn't want append entire makefile. it's 914 lines, i'd happy update question snippets if help.

update: here dependency generation rule & compile rule:

# # dependency generation rules #  define dependency-rules    $(subst .o,.d,$1): $2     $(cc) $(cflags) $(defines) $(incflags) $3 $(target_arch) -m $$< | \     $(sed) 's,\($$(notdir $$*)\.o\) *:,$$(dir $$@)\1 $$@: ,' > $$@.tmp     $(mv) $$@.tmp $$@  endef  %.d: %.cpp     $(cc) $(cflags) $(cppflags) $(target_arch) -m $< | \     $(sed) 's,\($(notdir $*)\.o\) *:,$(dir $@)\1 $@: ,' > $@.tmp     $(mv) $@.tmp $@

update 2: using @beta's suggestion, able parcel out dependency generation , makefile time 14.2% of overall compiling time. i'm going focus on minimizing header inclusion in c++ code first. both of suggestions!!

  1. it shouldn't difficult determine changes slowed down. have versions on past 3 years (i hope), , difference dramatic. try version 2 years ago. if it's taking long, binary search. automate process, have run overnight , give graph in morning, build time sampled each month past 36 months.
  2. if you're using gnumake (as hope), `make -n` print out commands would execute, without executing them. give of make time no compilation time.
  3. one of biggest sources of unnecessary build time (even bigger recursion, aren't using) unnecessary rebuilding, recompiling/relinking/whatever when don't need to. can because makefile doesn't handle dependencies correctly, or because c++ files `#include` headers recklessly, or cuda or fortran wouldn't know. run make twice in row, , see if on second pass. on makefile suspiciously huge prerequisite lists. have skillful programmer take @ few of source files, newer ones, , check unnecessary dependencies.

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