gnu make - variable target in a makefile -

i trying compile set of targets. seems first one. below cut down of makefile shows error.

  objects = abc def ghi   sources = abc.c def.c ghi.c    $(objects):     $(sources)           @echo target $@, source $< 

in shell,

  $ touch abc.c def.c ghi.c   $ make 

when run make following output:

  target abc, source abc.c 

so seems running first target.

if replace $< $^, output is:

  target abc, source abc.c def.c ghi.c 

my question, possible perform expansions on variables (%: %) pattern?

try this:

  objects = abc def ghi    all: $(objects)    $(objects):%:%.c           @echo target $@, source $< 

the trouble was

1. the default target (which make chooses if type `make`) first target in makefile, `abc`.
2. you made all sources prerequisites of every object. is, 3 sources prerequisites of `abc`. prerequisites of `def` , of `ghi`.